Microelectronic Devices (Excluding Hybrids)

Table A-38. Bi-Polar Beam Lead, ECL, All Linear and All MOS Devices - Generic Failure Rates, Environmental Factors and Failure Modes
Non- operational	Bipolar Beam Lead, ECL All Linear and MOS Devices	Operational
Base Failure Rate bfailures 106 hrs	Bipolar Beam Lead, ECL All Linear and MOS Devices	Base Failure Rate bfailures 106 hrs	Environmental Factors ( KE)					Predominant Failure Modes
GFP		G.1	G.2	S.1	S.2	A.1	A.2	Mode	% Factor
Ground Fixed Protected	Circuit Complexity	Ground Fixed	Ground Mobile	Ship Protected	Ship Exposed	Air Protected	Air Exposed	Mode	% Factor
0.005	1- 20 Gates	0.05	2.5	2.9	5.2	2.5	5.0
0.019	21- 50	0.19	1.8	2.3	4.8	1.8	4.2
0.031	51 -l00	0.31	1.7	2.2	4.8	1.7	4.2
0.082	101-500	0.82	1.6	2.1	4.8	1.6	3.9
0.14	50l -l000	1.40	1.5	2.0	4.6	1.5	3.8
0.31	1001-200	3.10	1.5	2.1	4.8	1.5	3.9
0.84	2001-3000	8.40	1.5	2.0	4.9	1.5	3.9	Loss of Output	90

Table A-38. Bi-Polar Beam Lead, ECL, All Linear and All MOS Devices - Generic Failure Rates, Environmental Factors and Failure Modes
2.30	3001-4000	23.00	1.6	2.0	4.8	1.6	3.9
6.2	4001-5001	62.00	1.6	2.1	4.8	1.6	3.9
	Read-only Memories (ROM)
0.009	<320 Bits	0.09	1.6	2.1	4.8	1.6	3.9	Open Input	10

Table A-38. Bi-Polar Beam Lead, ECL, All Linear and All MOS Devices - Generic Failure Rates, Environmental Factors and Failure Modes
0.013	321 - 576	0.13	1.5	2.1	4.8	1.5	3.9
0.02	577 - 1120	0.20	1.6	2.1	4.9	1.6	4.0
0.03	1121 - 2240	0.30	1.6	2.1	5.0	1.6	4.0
0.046	2241 - 5000	0.46	1.6	2.1	4.8	1.6	3.9
0.07	500l - 1l000	0.70	1.6	2.1	4.8	1.6	4.0
0.11	11001 - 17000	1.10	1.5	2.0	4.7	1.5	3.9
	Random Access Memories (RAM)
0.032	<320 Bits	0.32	1.6	2.1	4.8	1.6	3.9
0.046	321 - 576	0.46	1.5	2.1	4.8	1.5	3.9
0.070	577 - 1120	0.70	1.6	2.1	4.9	1.6	4.0
0.105	1121 - 2240	1.05	1.6	2.1	5.0	1.6	4.0
0.161	2241 - 5000	1.61	1.6	2.1	4.8	1.6	3.9
0.245	500l - l1000	2.45	1.6	2.1	4.8	1.6	4.0
0.385	11001 - 17000	3.85	1.5	2.0	4.7	1.5	3.9
0.032	<320 Bits	0.32	1.6	2.1	4.8	1.6	3.9
0.005 Linear	< 32 Transistors	0.05	2.9	3.1	5.2	2.9	5.2
0.011 Linear	33 - 100 Transistor	0.11	2.8	3.2	5.4	2.8	5.4

Table A-39. Bi-Polar Digital Devices (TM and DTL) - Generic Failure Rates, Environmental Factors and Failure Modes
Base Failure Rate bfailures 106 hrs		Base Failure Rate bfailures 106 hrs	Environmental Factors ( KE)					Predominant Failure Modes
GFP		G.1	G.2	S.1	S.2	A.1	A.2	Mode	% Factor
Ground Fixed Protected	Circuit Complexity	Ground Fixed	Ground Mobile	Ship Protected	Ship Exposed	Air Protected	Air Exposed	Mode	% Factor

Table A-39. Bi-Polar Digital Devices (TM and DTL) - Generic Failure Rates, Environmental Factors and Failure Modes
0.003	1- 20 Gates	0.03	3.1	3.2	4.1	3.1	4.8
0.006	21- 50	0.06	2.6	2.7	3.7	2.6	4.0
0.009	51 -l00	0.09	2.4	2.4	3.6	2.4	3.8
0.022	101-500	0.22	2.0	2.2	3.2	2.0	3.3
0.034	50l -l000	0.34	2.0	2.1	3.2	2.0	3.2
0.078	1001-200	0.78	1.9	2.2	3.2	1.9	3.2
0.210	2001-3000	2.10	1.9	2.1	3.2	1.9	3.2
0.570	3001-4000	5.70	1.9	2.1	3.2	1.9	3.2
1.600	4001-5001	16.00	1.9	2.1	3.1	1.9	3.1	High Output (1)	60
								Low Output (0)	30

Table A-39. Bi-Polar Digital Devices (TM and DTL) - Generic Failure Rates, Environmental Factors and Failure Modes
	Read-only Memories (ROM)

Table A-39. Bi-Polar Digital Devices (TM and DTL) - Generic Failure Rates, Environmental Factors and Failure Modes
0.002	<320 Bits	0.02	1.9	2.2	3.2	1.9	3.2	Open Input	10

Table A-39. Bi-Polar Digital Devices (TM and DTL) - Generic Failure Rates, Environmental Factors and Failure Modes
0.003	321 - 576	0.03	2.0	2.2	3.3	2.0	3.3
0.005	577 - 1120	0.05	1.9	2.1	3.3	1.9	3.3
0.008	1121 - 2240	0.08	2.0	2.2	3.2	2.0	3.3
0.012	2241 - 5000	0.12	2.0	2.2	3.2	2.0	3.2
0.018	500l - 1l000	0.18	2.1	2.3	3.3	2.1	3.4
0.028	11001 - 17000	0.28	2.1	2.2	3.3	2.1	3.4
	Random Access Memories (RAM)
0.007	<320 Bits	0.07	1.9	2.2	3.2	1.9	3.2
0.011	321 - 576	0.11	2.0	2.2	3.3	2.0	3.3
0.018	577 - 1120	0.18	1.9	2.1	3.3	1.9	3.3
0.028	1121 - 2240	0.28	2.0	2.2	3.2	2.0	3.3
0.042	2241 - 5000	0.42	2.0	2.2	3.2	2.0	3.2
0.063	500l - 1l000	0.63	2.1	2.3	3.3	2.1	3.4
0.098	11001 - 17000	0.96	2.1	2.2	3.3	2.1	3.4

Table A-40. Summary of Failure Rate Models, Factors and Data Tables

Linear

Digital

Memories RAMS and CAMS; ROMS and PROMS Static and dynamic shift registers

Small and Medium Scale Integration (SS/MSI) Less than 100 gates or 400 transistors

Large Scale Integration (LSI) and Micro- processor Devices More than 100 gates or 400 transistors (See Note 1 below)

λp = KQ(C1)(KT+C2KE

λp = KQKP(C1)(KT+C2KE

Where:

λp= Total failure rate of the device in failures/106 operating hours.

KQ = The Quality factor, obtained from Table A-41 for all devices.

KE = The Environmental factor, obtained from Table A-42 for all devices.

KT = The Temperature Acceleration factor, obtained from Table A-43 for all devices.

C1 and C2 = The Circuit Complexity failure rates, based on the number of transistors for linear devices, the number of gates for digital devices and the number of bits for memories. They are obtained from:

• Table A-44 for linear devices.

• Table A-45 for digital SSI/MSI devices.

• Table A-46 for digital LSI and microprocessor devices.

• Table A-47 for memories.

KP = The Pin factor, obtained from Table A-45 through Table A-47 for devices as shown above.

A J-K (grating) or R-S (set and re-set) flip-flop is equivalent to 8 gates when used as part of a complex circuit.

For shift registers larger than dual 8-bit, the RAM model should be used. For smaller shift registers, the digital SSM/MSI model should be used.

Table A-41. Quality Factors for Microelectronic Devices
Screening Level	BS 9000
Screening Level	S1	S2	S3	S4	Full Assessment
Quality Factor, KQ	0.5	1.0	2.5	5.0	8.0

Table A-42. Environmental Factors for Microelectronic Devices

Operational

Environment

(See Note1 below)

KE

Ground Fixed

G1

1.0

Ground Mobile

G2

4.0

Ship Protected

S1

4.0

Ship Exposed

S2

5.0

Air Protected

A1

4.0

Air Exposed

A2

6.0

The environments are described in Table A-57.

Table A-43. Temperature Acceleration Factors Vs. Junction Temperature

Tj(ºC)

KT1

KT2

Tj(ºC)

KT1

KT2

Tj(ºC)

KT1

KT2

Tj(ºC)

KT1

KT2

25

.10

51

.36

.89

77

1.1

5.7

103

2.8

29.0

27

.11

.12

53

.40

1.00

79

1.2

6.5

105

3.0

32.0

29

.12

.14

55

.44

1.20

81

1.3

7.5

110

3.6

42.0

31

.14

.17

57

.48

1.40

83

1.4

8.5

115

4.2

56.0

33

.15

.20

59

.52

1.60

85

1.5

9.6

120

4.9

73.0

35

.17

.24

61

.57

1.90

87

1.6

11.0

125

5.7

94.0

37

.19

.29

63

.62

2.20

89

1.7

12.0

135

7.6

155.0

39

.21

.34

65

.67

2.50

91

1.8

14.0

145

10.0

250.0

41

.23

.40

67

.73

2.90

93

2.0

16.0

155

13.0

393.0

43

.25

.47

69

.79

3.30

95

2.1

18.0

165

17.0

607.0

45

.28

.56

71

.86

3.80

97

2.3

20.0

175

22.0

918.0

47

.30

.65

73

.93

4.40

99

2.5

23.0

49

.33

.76

75

1.00

5.00

101

2.6

25.0

1. KT1 is applicable to Bipolar digital devices, i.e., TTL and DTL, and to I2L. It does not apply to Bipolar Beam Lead and Bipolar ECL. (See Note 2.)

2. KT2 is applicable to Bipolar and MOS Linear, Bipolar Beam Lead, Bipolar ECL and all other MOS devices.

3. In the table above, Tj is the worst-case junction temperature in °C . If Tj is unknown, use the following approximations for all microcircuit types except low power TTL andMOS:

Tj = ambient T(°C) + 10°C if the number of gates < 30 or the number of linear circuit transistors < 120.

Tj = ambient T(°C) + 25°C if the number of gates > 30 or the number of linear circuit transistors > 120 and for all memories.

For low power TTL, MOS and I2L, use the following approximations if Tj is unknown:

Tj = ambient T(°C) + 5°C if the number of gates < 30 or the number of linear circuit transistors < 120.

Tj = ambientT(°C) + 13°C if the number of gates > 30 or the number of linear circuit transistors > 120 and for all memories.

Table A-44. Linear Devices - Complexity Failure Rates
No. of Transistors	Failure/106 hrs		No. of Transistors	Failure/106 hrs		No. of Transistors	Failure/106 hrs
No. of Transistors	C1	C2	No. of Transistors	C1	C2	No. of Transistors	C1	C2
4	.0016	.0056	64	.013	.025	148	.025	.040
8	.0027	.0081	68	.014	.026	156	.026	.041
12	.0037	.010	72	.015	.027	164	.027	.042
16	.0046	.012	76	.015	.028	172	.028	.043
20	.0055	.013	80	.016	.029	180	.029	.045
24	.0063	.015	84	.016	.029	188	.030	.046
28	.0071	.016	88	.017	.030	196	.031	.047
32	.0079	.017	92	.618	.031	204	.032	.048
36	.0086	.018	96	.018	.032	220	.034	.050
40	.0093	.020	100	.019	.032	236	.036	.052
44	.010	.021	108	.020	.034	252	.038	.054
48	.011	.022	116	021	.035	268	.040	.055
52	.011	.023	124	.022	.036	284	.042	.057
56	.012	.024	132	.023	.038	300	.043	.059
60	.013	.024	140	.024	.039

Table A-45. SSI/SMI Devices - Complexity Failure Rates and Pin Factors

No. of Gates

Failure/108 hrs

No. of Gates

Failure/108 hrs

No, of Gates

Failure/108 hrs

C1

C2

C1

1

.0013

.0039

30

.013

60

.021

.017

2

.0021

.0050

32

.013

62

.021

.017

4

.0033

.0064

34

.014

64

.022

.017

6

.0043

.0074

36

.015

.014

66

.022

.018

8

.0053

.0082

38

.015

.014

68

.022

.018

10

.0061

.0089

40

.016

.015

70

.023

.018

12

.0069

.0095

42

.016

.015

72

.023

.018

14

.0077

.010

44

.017

.015

74

.024

.018

16

.0084

.011

46

.017

.015

76

.024

.018

18

.0091

.011

48

.018

.016

78

.025

.019

20

.0098

.011

50

.018

.016

80

.025

.019

22

.010

.012

52

.019

.016

85

.026

.019

24

.011

.012

54

.019

.016

90

.027

.020

26

.012

.013

56

.020

.017

95

.028

.020

28

.012

.013

58

.020

.017

99

.029

.020

The pin factor, KP\, is based upon the number of pins (package leads) and is:

No. of Pins	KP
< 24	1.0
24 to 40	1.1
41 to 64	1.2
>64	1.3

Table A-46. LSI Devices - Complexity Failure Rates and Pin Factors

No. of Gates

Failure/108 hrs

No. of Gates

Failure/108 hrs

No, of Gates

Failure/108 hrs

C1

C2

C1

100

.029

.020

950

.13

.046

4200

3.4

1.1

150

.038

.024

1000

.14

.046

4400

4.2

1.4

200

.047

.026

1200

.17

.057

4600

5.1

1.7

250

.054

.028

1400

.21

.069

4800

6.2

2.1

300

.061

.030

1600

.25

.085

5000

7.6

2.5

350

.068

.032

1800

.31

.100

5200

9.2

3.1

400

0.75

.032

2000

.38

.130

5400

11.0

3.8

450

.081

.035

2200

.46

.150

5600

14.0

4.6

500

.087

.036

2400

.56

.190

5800

17.0

5.6

550

.092

.037

2600

.69

.230

6000

21.0

6.9

600

.098

.039

2800

.84

.280

6200

25.0

8.4

650

.100

.040

3000

1.0

.340

6400

31.0

10.0

700

.110

.041

3200

1.3

.420

6600

37.0

13.0

750

.110

.042

3400

1.5

.510

6800

46.0

15.0

800

.120

.043

3600

1.9

.630

7000

56.0

19.0

850

.120

.044

3800

2.3

.760

900

.130

.045

4000

2.8

.930

The pin factor, KP\, is based upon the number of pins (package leads) and is:

No. of Pins	KP
< 26	1.0
26 to 64	1.1
>64	1.2

Table A-47. Memories - Complexity Failure Rates and Pin Factors

No. of Bits

ROMS

(including PROMS)

ROMS

(including PROMS)

C1

C2

C1

16

.0015

.00048

.0053

.00l7

32

.0023

.00075

.0080

.0026

64

.0035

.0012

.012

.0041

128

.0053

.0018

.019

.0064

256

.0081

.0029

.028

.010

320

.0092

.0033

.032

.011

512

.012

.0045

.043

.016

576

.013

.0049

.046

.017

1024

.019

.0070

.065

.024

1120

.020

.0075

.069

.026

1280

.021

.0081

.074

.028

2048

.028

.011

.099

.038

2240

.030

.012

.10

.040

2560

.032

.013

.11

.044

4096

.043

.017

.15

.059

8192

.065

.027

.23

.093

9216

.070

.029

.24

.10

10240

.075

.031

.26

.11

12288

.083

.035

.29

.12

14848

.093

.040

.33

.14

16384

.099

.042

.35

.14

The pin factor, KP\, is based upon the number of pins (package leads) and is:

No. of Pins	KP
≤ 24	1.0
>24	1.2