Failure Rate Mode General Expression
The Parts Stress Analysis models are based on the concept that the overall failure rate of an integrated circuit is the sum of two failure rate contributions:
• A contribution (C1) due to failure mechanisms that are accelerated by temperature and electrical bias.
• A contribution (C2) due to failure mechanisms that result from indirect mechanical stresses and also from indirect mechanical stresses such as those caused by thermal expansion.
C1 and C2 are termed Complexity Failure Rates because they are related to the complexity of any particular device. In effect, they represent the base failure rate of the device.
To adjust the two failure rate contributions (C1 and C2) for the particular condition in which a device is to be applied, the base failure rates are weighted by factors, which are related to the operating conditions. The C1 failure rate is adjusted by temperature acceleration factor (KT), which depends upon junction Temperature ( Tj) and the C2 failure rate by an environmental factor (KE), which depends upon th particular operational environment in which the device is to be used.
Other considerations affecting the operational failure rate of a device are the number of active current-carrying pins and the quality screening and inspection process applied during manufacture. These are taken into account by means of further weighting factors, and .
From the above considerations, the predicted failure rate (λp) of a microelectronic
Where:
λp= The predicted operational failure rate (in failures/106 component operating hours) of a microelectronic device under stated environmental and operating conditions.
C1 and C2 = The operational base failure rates for the particular device.
KT=The temperature acceleration factor for the device.
KE= The environmental factor for the operational environment of the device.
Kp= The active pin factor for the device.
KQ= The quality factor for the screening level under which the device is procured.