Windchill Risk and Reliability Desktop Help > Windchill Prediction > Part Parameters Required for Predictions > MIL-HDBK-217 Part Parameters > MIL-HDBK-217 Temperature Calculations > Thermal Resistance Values for Integrated Circuits
Thermal Resistance Values for Integrated Circuits
MIL-M-38510H Appendix C supplies maximum thermal resistance values from the junction to the case for integrated circuits. The following table provides these Theta JC values for your convenience. If the device die size is greater than 14400 sq. mil or the thermal resistances cannot be determined, use the values given in the supplementary table provided below.
Description
Package Size
Max Theta JC
Flatpack (FP)
10, 14, 16, 18, 20, 24, 28 lead
22
Dual-In-Line Package (DIP)
8, 14, 16, 18, 20, 22, 24, 28, 40, 50, 64 lead
28
Can
8 lead
70
Rect. Leadless Chip Carrier (LCC)
10, 12 lead
65
Square Leadless Chip Carrier (LCC)
16, 20, 24, 28, 44, 52, 68, 84 terminal
18, 20, 28, 32 terminal
20
20
J Bend Leaded Chip Carrier (JCC)
44, 68, 84 terminal
20
Gullwing Leaded Chip Carrier (GCC)
44, 68, 84 terminal
20
Unformed-Lead Chip Carrier
84, 100, 132, 144, 172, 196 terminal
20
Pin Grid Array (PGA)
81, 100, 121, 144, 169, 196, 225, 256, 289, 324, 361, 400 pin
20
The following table provides the maximum Theta JC values that should be used for device die sizes greater than 14400 sq. mil and the worst case Theta JC values that should be used when thermal resistance cannot be determined.
Package Type (Ceramic Only)
Die Area > 14,400 sq mil
Worst Case Default
Dual-In-Line
11
28
Flat Package
10
22
Chip Carrier
10
20
Pin Grid Array
10
20
Can
--
70
MIL-HDBK-217 Temperature Calculations